Circuit design of a novel adaptable and reliable L1 data cache

This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. Depending on the supply voltage level, Adapcache defines three operating modes: In high supply voltages, Adapcache provides reliability through single-bit parity. In middle range of supply voltages, Adapcache writes data to two separate cache-lines simultaneously in order to use one line for error recovery when the other line is faulty. In near threshold supply voltages, Adapcache writes data to three separate cache-lines simultaneously in order to provide the correct data based on bitwise majority voter. We design and simulate one embodiment of the Adapcache as a 64-KB L1 data cache with 45-nm CMOS technology at 2GHz processor frequency for almost nominal supply voltages (1V-0.6V), at 900MHz for middle supply voltages (0.6V-0.4V), and at 400MHz for near threshold supply voltages (0.4V-0.32V). According to our experimental results, the energy reduction and latency as well as cache capacity usage are improved compared to typical previous proposals, Triple Modular Redundancy (TMR) and Double Modular Redundancy (DMR) techniques and also to the state of the art proposal, Parichute Error Correction Code (ECC).Postprint (published version

System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications

Cache memory circuits are one of the concerns of computing systems, especially in terms of power consumption, reliability, and high performance. Voltage-scaling techniques can be used to reduce the total power consumption of the caches. However, aggressive voltage scaling significantly increases the probability of memory failure, especially in environments with high radiation levels, such as space. It is, therefore, important to deploy techniques to deal with reliability issues along with voltage scaling. In this chapter, we present a system-scenario methodology for radiation-hardened memory design to keep the reliability during voltage scaling. Although any SRAM array can benefit from the design, we frame our study on the recently proposed radiation-hardened cell, Nwise, which provides high level of tolerance against single event and multi event upsets in memories. To reduce the power consumption while upholding reliability, we leverage the system-scenario-based design methodology to optimize the energy consumption in applications, where system requirements vary dynamically at run time. We demonstrate the use of the methodology with a use case related to satellite systems and solar activity. Our simulations show that we achieve up to 49.3% power consumption saving compared to using a cache design with a fixed nominal power supply level

An Energy-Efficient Design Paradigm for a Memory Cell Based on Novel Nanoelectromechanical Switches

In this chapter, we explain NEMsCAM cell, a new content-addressable memory (CAM) cell, which is designed based on both CMOS technologies and nanoelectromechanical (NEM) switches. The memory part of NEMsCAM is designed with two complementary nonvolatile NEM switches and located on top of the CMOS-based comparison component. As a use case, we evaluate first-level instruction and data translation lookaside buffers (TLBs) with 16 nm CMOS technology at 2 GHz. The simulation results demonstrate that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), standby mode (by 53.9%), write operation (by 41.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead.We thank all anonymous reviewers for their insightful comments. This work is supported in part by the European Union (FEDER funds) under contract TIN2012-34557, and the European Union’s Seventh Framework Programme (FP7/2007-2013) under the ParaDIME project (GA no. 318693)Postprint (author's final draft

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32-KB dual-versioning L1 data cache with 45nm CMOS technology at 2GHz processor frequency and 1V supply voltage, which we describe in detail. We also introduce three well-known use cases that make use of optimistic concurrency execution and that can benefit from our proposed design. Moreover, we evaluate one of the use cases to show the impact of the dual-versioning cell in both performance and energy consumption. Our experiments show that large speedups can be achieved with acceptable overall energy dissipation.Postprint (published version

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

In the electronics space industry, memory cells are one of the main concerns, especially in term of reliability, since radiation particles may hit cell nodes and disturb the state of the cell, possibly causing fatal errors. In this paper we propose the Nwise SRAM cell, an area-efficient and highly reliable radiation hardened memory cell for use in high-density memories for space applications. Simulations confirm that the proposed Nwise cell is fully tolerant to single event upsets (SEU) in any one of its nodes regardless of upset polarity. Meanwhile, compared with the RHBD-10T cell, the latest area-efficient radiation hardened memory cell, it has higher robustness: the minimum critical charge of Nwise is 4.1× higher than the minimum critical charge of the RHBD-10T cell. It also shows 23% and 12% improvements in read and write static noise margin (SNM). Furthermore, compared with RHBD-10T, up to 18.4% and 7.0% power savings are obtainable during write and read operations respectively. Nwise is about 2.28× faster than RHBD-10T during the more frequent read operation, with a similar penalty in write time. Finally, Nwise is the first proposed high density and reliable radiation hardened memory cell that has been designed using the 28nm FD-SOI technology node. Index Terms—space applications, radiation hardening, single event upset (SEU), multiple event upset (MEU), SRAM design, 28nm FD-SOI, reliability, soft errors, Nwise cel

Circuit design of a dual-versioning L1 data cache

This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors that implement optimistic concurrency proposals. In this cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same logical data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32 KB dual-versioning L1 data cache and introduce three well-known use cases that make use of optimistic concurrency execution that can benefit from our proposed design. © 2011 Elsevier B.V. All rights reserved.This work is supported by the cooperation agreement between the Barcelona Supercomputing Center and Microsoft Research, by the Ministry of Science and Technology of Spain and the European Union (FEDER funds) under contracts TIN2007-60625 and TIN2008-02055-E, by the European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC) and by the European Commission FP7 project VELOX (216852).Peer Reviewe

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead.We thank all anonymous reviewers for their insightful comments. This work is supported in part by the European Union (FEDER funds) under contract TIN2012-34557, and the European Union’s Seventh Framework Programme (FP7/2007-2013) under the ParaDIME project (GA no. 318693

Comparison of insulin resistance indices in predicting albuminuria among patients with type 2 diabetes

Abstract Purpose Diabetes is the leading cause of kidney disease. Up to 40% of the population with diabetes experience diabetic kidney disease (DKD). The correlation of DKD with insulin resistance (IR) indices has been shown in previous studies. In this study, the objective was to evaluate surrogate IR indices, including the Triglyceride-Glucose (TyG) index, Visceral Adiposity Index (VAI), Lipid Accumulation Product (LAP), and Homeostasis Model Assessment of Insulin Resistance (HOMA-IR) to find the most valuable index for the correlation between albuminuria and IR in the type 2 diabetes (T2D) population. Albuminuria is defined as urine albumin excretion of > 30 mg/day. Methods In this cross-sectional study, 2934 participants were enrolled and evaluated for urinary albumin excretion, and albuminuria was detected in 526 of the entries. The logistic regression models and Receiver Operating Characteristic (ROC) curve analysis were performed to assess the relationship of TyG index, VAI, LAP, and HOMA-IR's with albuminuria in patients with T2D. Results The TyG index had the highest association (OR 1.67) with the presence of albuminuria in patients with T2D, followed by HOMA-IR (OR 1.127), VAI (OR 1.028), and LAP (OR 1.004). These four indices remained independent after adjustment for multiple confounders. Based on the ROC curve, TyG revealed the best area under the curve (AUC) for revealing albuminuria with sufficient accuracy (AUC: 0.62) in comparison with other measured indices. The calculated TyG index cut-off point for the presence of albuminuria was 9.39. Conclusion Among the indices, TyG index had the most significant correlation with albuminuria in patients with T2D